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ADT7475
Table 26. INTERRUPT MASK REGISTER 1
(REG. 0X74)
Once Pin 9 is configured as THERM, it must be enabled
(Bit 1, Configuration Register 3 (0x78)).
Bit
Mnemonic
Description
THERM as an Input
7 OOL 1 masks SMBALERT for any alert
condition flagged in Interrupt Status
Register 2.
6 R2T 1 masks SMBALERT for Remote 2
temperature.
5 LT 1 masks SMBALERT for Local
temperature.
4 R1T 1 masks SMBALERT for Remote 1
temperature.
2 V CC 1 masks SMBALERT for the V CC
channel.
0 V CCP 1 masks SMBALERT for the V CCP
channel.
Table 27. INTERRUPT MASK REGISTER 2
(REG. 0X75)
When THERM is configured as an input, the user can time
assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge
system performance.
The user can also set up the ADT7475 so that, when the
THERM pin is driven low externally, the fans run at 100%.
The fans run at 100% for the duration of the time that the
THERM pin is pulled low. This is done by setting the
BOOST bit (Bit 2) in Configuration Register 3 (0x78) to 1.
This works only if the fan is already running, for example,
in manual mode when the current duty cycle is above 0x00
or in automatic mode when the temperature is above T MIN .
If the temperature is below T MIN or if the duty cycle in
manual mode is set to 0x00, pulling the THERM low
externally has no effect. See Figure 26 for more information.
Bit
Mnemonic
Description
7
6
5
4
3
2
D2
D1
FAN4
FAN3
FAN2
FAN1
1 masks SMBALERT for Diode 2 errors.
1 masks SMBALERT for Diode 1 errors.
1 masks SMBALERT for Fan 4 failure. If
the TACH4 pin is being used as the
THERM input, this bit masks
SMBALERT for a THERM event.
1 masks SMBALERT for Fan 3.
1 masks SMBALERT for Fan 2.
1 masks SMBALERT for Fan 1.
T MIN
THERM
1 OVT 1 masks SMBALERT for
overtemperature (exceeding THERM
limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by
default. Pin 5 or Pin 9 can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
Table 28. CONFIGURING PIN 5 AS SMBALERT
OUTPUT
Register Bit Setting
Configuration Register 3 <0> ALERT Enable = 1
(Reg. 0x78)
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7475 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user
chooses the required functionality by setting Bit 0 and Bit 1
of Configuration Register 4 (0x7D).
Table 29. PIN 9 CONFIGURATION
THERM ASSERTED TO LOW AS THERM ASSERTED TO LOW AS
AN INPUT: FANS DO NOT GO AN INPUT: FANS DO NOT GO TO
TO 100% BECAUSE TEMPERATURE 100% BECAUSE TEMPERATURE
IS BELOW T MIN IS ABOVE T MIN AND FANS ARE
ALREADY RUNNING.
Figure 26. Asserting THERM Low as an Input in
Automatic Fan Speed Control Mode
THERM Timer
The ADT7475 has an internal timer to measure THERM
assertion time. For example, the THERM input can be
connected to the PROCHOT output of a Pentium ? 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7475’s
THERM input and stopped when THERM is un-asserted.
The timer counts THERM times cumulatively, that is, the
timer resumes counting on the next THERM assertion. The
THERM timer continues to accumulate THERM assertion
times until the timer is read (it is cleared on read) or until it
reaches full scale. If the counter reaches full scale, it stops at
that reading until cleared.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Function
TACH4
THERM
SMBALERT
GPIO
The 8-bit THERM timer status register (0x79) is designed
so that the Bit 0 is set to 1 o n the first THERM assertion. Once
the cumulative THERM assertion time has exceeded
45.52 ms, Bit 1 of the THERM timer is set and Bit 0 becomes
the LSB of the timer with a resolution of 22.76 ms, see
Figure 27.
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